-- Copyright (C) 2018  Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Intel Program License 
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors.  Please
-- refer to the applicable agreement for further details.

library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_syn_attributes.all;

entity TrafficLight is
	port
	(
-- {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!

		i_sys_clk : in std_logic;
		i_sys_emergency : in std_logic;
		i_sys_rst : in std_logic;
		o_ew_green : out std_logic;
		o_ew_red : out std_logic;
		o_ew_tens_a : out std_logic;
		o_ew_tens_b : out std_logic;
		o_ew_tens_c : out std_logic;
		o_ew_tens_d : out std_logic;
		o_ew_tens_e : out std_logic;
		o_ew_tens_f : out std_logic;
		o_ew_tens_g : out std_logic;
		o_ew_units_a : out std_logic;
		o_ew_units_b : out std_logic;
		o_ew_units_c : out std_logic;
		o_ew_units_d : out std_logic;
		o_ew_units_e : out std_logic;
		o_ew_units_f : out std_logic;
		o_ew_units_g : out std_logic;
		o_ew_yellow : out std_logic;
		o_ns_green : out std_logic;
		o_ns_red : out std_logic;
		o_ns_tens_a : out std_logic;
		o_ns_tens_b : out std_logic;
		o_ns_tens_c : out std_logic;
		o_ns_tens_d : out std_logic;
		o_ns_tens_e : out std_logic;
		o_ns_tens_f : out std_logic;
		o_ns_tens_g : out std_logic;
		o_ns_units_a : out std_logic;
		o_ns_units_b : out std_logic;
		o_ns_units_c : out std_logic;
		o_ns_units_d : out std_logic;
		o_ns_units_e : out std_logic;
		o_ns_units_f : out std_logic;
		o_ns_units_g : out std_logic;
		o_ns_yellow : out std_logic
-- {ALTERA_IO_END} DO NOT REMOVE THIS LINE!

	);

-- {ALTERA_ATTRIBUTE_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_ATTRIBUTE_END} DO NOT REMOVE THIS LINE!
end TrafficLight;

architecture ppl_type of TrafficLight is
component div_clk_50M
 port(
		i_sys_clk:in std_logic;
		i_sys_rst:in std_logic;
		--i_sys_emergency:in std_logic;
		o_div_clk:out std_logic
	);
end component;

component disp_tube
  port(
		i_time_val:in std_logic_vector(3 downto 0);
		i_sys_rst:in std_logic;
		i_sys_en:in std_logic;
		a,b,c,d,e,f,g:out std_logic
		--o_tube_disp_val:out std_logic_vector(6 downto 0)
	);
end component;

component CD25s
  port(
		i_div_clk:in std_logic;								--1hz时钟输入
		i_sys_rst:in std_logic;								--复位
		i_sys_emergency:in std_logic;						--紧急状态
		o_tim_tens:out std_logic_vector(3 downto 0);	--输出倒计时十位BCD
		o_tim_units:out std_logic_vector(3 downto 0);--输出倒计时个位BCD
      o_tim_carry:out std_logic							--输出进位
	);
end component;

component control
  port(
		i_sys_rst:in std_logic;
		i_div_clk:in std_logic;									--1hz时钟输入
		i_tim_tens:in std_logic_vector(3 downto 0);		--输入倒计时十位BCD
		i_tim_units:in std_logic_vector(3 downto 0);		--输入倒计时个位BCD
      i_tim_carry:in std_logic;								--输入进位
		i_sys_emergency:in std_logic;							--紧急状态
		o_tim_tens_ew:out std_logic_vector(3 downto 0);	--输出东西倒计时十位BCD
		o_tim_units_ew:out std_logic_vector(3 downto 0);--输出东西倒计时个位BCD
		o_tim_tens_ns:out std_logic_vector(3 downto 0);	--输出南北倒计时十位BCD
		o_tim_units_ns:out std_logic_vector(3 downto 0);--输出南北倒计时个位BCD
		o_seg_en:out std_logic;
		o_ew_red,o_ew_yellow,o_ew_green,o_ns_red,o_ns_yellow,o_ns_green:out std_logic--输出东西南北红绿灯
		
	);
end component;

-- {ALTERA_COMPONENTS_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_COMPONENTS_END} DO NOT REMOVE THIS LINE!

-- {ALTERA_INSTANTIATION_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_INSTANTIATION_END} DO NOT REMOVE THIS LINE!


end ppl_type;
